Significant Publications

No Authors Tile of the paper Journal / Conference Details Paper Link
1 Anil Kumar and Basavaraj Talawar Floorplan Based Performance Estimation of Network-on-Chips using Regression Techniques 5th international Conference for Convergence In Technology (I2CT 2019) 29-31 March 2019, The Gateway Hotel(TAJ), Pune, India. PDF
2 Prabhu Prasad,Khyamling Parane and Basavaraj Talawar Analysis of cache behaviour and software optimizations for faster on-chip network simulations International Journal of System Assurance Engineering and Management, Springer PDF
3 Prabhu Prasad,Khyamling Parane and Basavaraj Talawar High-Performance NoC Simulation Acceleration frameworkemploying the Xilinx DSP48E1 blocks 2019 International Symposium on VLSI Design, Automation and Test (2019 VLSI-DAT)April 22-25, 2019| at Ambassador Hotel, Hsinchu, Taiwan PDF
4 Khyamling Parane,Prabhu Prasad and Basavaraj Talawar Design of an Adaptive and Reliable Network on Chip router architecture using FPGA 2019 International Symposium on VLSI Design, Automation and Test (2019 VLSI-DAT)April 22-25, 2019| at Ambassador Hotel, Hsinchu, Taiwan PDF
5 Prabhu Prasad,Khyamling Parane and Basavaraj Talawar High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs 20th International Symposium on Quality Electronic Design(ISQED 2019) March 6 – 7, 2019 | Santa Clara Califonia, USA. PDF
6 Anil Kumar and Basavaraj Talawar UPM-NoC: Learning Based Framework to Predict Performance Parameters of Mesh Architecture of On-Chip Networks Intelligent Computing Techniques For Smart Energy Systems(ICTSES'18) 22-23 December 2018, Manipal University Jaipur, Jaipur, India PDF
7 Ujjwal Pasupulety, Bheemappa Halavar and Basavaraj Talawar Thermal Aware Design for Through- Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures 8th Int'l Symp. on Embedded Computing & System Design (ISED 2018), 13-15, December, 2018, CUSAT, Kochi, India PDF
8 G. S. Sangeetha, Vignesh Radhakrishnan, Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA 8th Int'l Symp. on Embedded Computing & System Design (ISED 2018), 13-15, December, 2018, CUSAT, Kochi, India PDF
9 Bheemappa Halavar and Basavaraj Talawar OP3DBFT: A Power and Performance Optimal 3D BFT NoC Architecture Intl. Conference on Intelligent Systems Design and Applications (ISDA 2018), 6-8 December, 2018, VIT, Vellore, India. PDF
10 Bheemappa Halavar, Ujjwal Pasupulety and Basavaraj Talawar Extending BookSim2.0 and HotSpot6.0 for power,performance and thermal evaluation of 3DNoC architectures Journal of Simulation Modelling Practice and Theory PDF
11 Khyamling Parane, Prabhu Prasad B M and Basavaraj Talawar YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs Journal of Circuits, Systems and Computers, World Scientific, 2018 PDF
12 Pramod Yelmewad, Basavaraj Talawar Parallel Iterative Hill Climbing Algorithm to Solve TSP on GPU Concurrency Computation Practice and Experience, Wiley Publication, 2018 PDF
13 Pramod Yelmewad, Basavaraj Talawar GPU-based Iterative Hill Climbing Algorithm to Solve Symmetric Salesman Problem HPC and Big Data: Convergence and Ecosystem, IOS Press, Amsterdam, Book Series "Advances in Parallel Computing" PDF
14 Ujjwal Pasupulety, Bheemappa Halavar and Basavaraj Talawar Accurate Power and Latency Analysis of a Through-Silicon Via (TSV) ICACCI'18, PES Institute of Technology, South Campus, Bangalore, India-2018 PDF
15 Anil Kumar and Basavaraj Talawar Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks 11th IC3 2018, Jaypee Institute of Information Technology, Noida, U.P., India PDF
16 Bheemappa Halavar and Basavaraj Talawar Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-Chip SPCOM 2018, Indian Institute of Science, Bangalore, India PDF
17 Pramod Yelmewad and Basavaraj Talawar Near Optimal Solution for Traveling Salesman Problem using GPU IEEE CONECCT 2018, March., 16-17, IISc Bangalore, India. PDF
18 Bheemappa Halavar and Basavaraj Talawar Accurate Performance Analysis of 3D Mesh Network on Chip Architectures IEEE CONECCT 2018, March., 16-17, IISc Bangalore, India. PDF
19 Khyamling Parane, Prabhu Prasad and Basavaraj Talawar FPGA based NoC Simulation Acceleration Framework Supporting Adaptive Routing IEEE CONECCT 2018, March., 16-17, IISc Bangalore, India. PDF
20 Pramod Yelmewad, Param Hanji, Amogha Udupa, Parth Shah and Basavaraj Talawar Parallel Computing for Iterative Hill Climbing Algorithm to solve TSP 24th HiPC 2017, Student Research Symposium, Jaipur, India. PDF
21 Prabhu Prasad, Khyamling Parane and Basavaraj Talawar YaNoC: Yet another Network-on-Chip Simulation Acceleration Engine using FPGAs 31st International Conference on Vlsi Design, January 8-10, 2018, Pune, India. PDF
22 Khyamling Parane, Prabhu Prasad and Basavaraj Talawar FPGA based simulation acceleration for Network-on-Chips INDOSYS 2017, IIT Bombay, India. PDF
23 Ankur Anandapu and Basavaraj Talawar Fast Large Graph Algorithms on GPU 23rd HiPC 2016, Student Research Symposium, Hyderabad, India PDF
24 Khyamling Parane, Prabhu Prasad and Basavaraj Talawar On-Chip Network Simulation Accelaration Using FPGAs 23rd HiPC 2016, Student Research Symposium, Hyderabad, India PDF
25 Anagh Singh, Anamik Sarvaiya and Basavaraj Talawar HiMesh: A Low Power High Perfomrance Improved Architecture for 3-D On-Chip Networks 23rd HiPC 2016, Student Research Symposium, Hyderabad, India PDF
26 Khyamling Parane, Prabhu Prasad and Basavaraj Talawar Cache Analysis and Software Optimizations for Faster On-Chip Network Simulations 11th Intl. Conf. on Industrial and Information Systems 2016, IIT Roorkee, Uttarakhand, India PDF
27 Aditya H K Upadhya, Basavaraj Talawar and Jeny Rajan GPU Implementation of Non-Local Maximum Likelihood Estimation Method for Denoising Magnetic Resonance Images Journal of Real-Time Image Processing (JRTIP), Springer, Jan 2016 PDF
28 Basavaraj Talwar A Crossbar Interconnection Network in DNA 14th IEEE International Workshop on HiCOMB 2015, IPDPS 2015 Workshops PDF
29 Avinash Kamath, Gaurangi Saxena, and Basavaraj Talawar Analysis of Ring Topology for NoC Architecture CoCoNet 2015, Trivandrum, Kerala, India. PDF
30 Vikas B, Basavaraj Talawar On the cache behavior of SPLASH2 Benchmarks on ARM and ALPHA processors in Gem5 Full System Simulator Intl. Conf. on Eco-friendly Computing and Communication Systems (ICECCS), December 18-21, 2014 PDF
31 Basavaraj Talwar and Bharadwaj Amrutur Traffic Engineered NoC for Streaming Applications Microprocessors & Microsystems, Elsevier, Vol. 37, Issue 3, May 2013, Pages 333-344 PDF