News @ SPARK


(*) Congrats to Khyamling Parane, Prabhu Prasad B M for their paper acceptance(poster): "FLNoC - FPGA based Network-on-Chip framework supporting Low latency router architecture", 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018) Co-located with Embedded Systems Week (ESWEEK) October 4 – 5, 2018 | Torino, Italy.

(*) Congrats to Pramod Yelmewad for their paper acceptance: "GPU-based Iterative Hill Climbing Algorithm to Solve Symmetric Salesman Problem", HPC and Big Data: Convergence and Ecosystem, IOS Press, Amsterdam, Book Series "Advances in Parallel Computing".

(*) Congrats to Ujjwal Pasupulety, Bheemappa Halavar for their paper acceptance: "Accurate Power and Latency Analysis of a Through-Silicon Via (TSV)", 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI'18), 19--22, September, 2018, PES Institute of Technology, South Campus, Bangalore, India.

(*) Congrats to Anil Kumar for their paper acceptance: "Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks", 11th Intl. Conference on Contemporary Computing, IC3 2018, 2 -- 4, Augst, 2018, Jaypee Institute of Information Technology, Noida, U.P., India.

(*) Congrats to Bheemappa Halavar for their paper acceptance: "Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-Chip", Intl. Conference on Signal Processing and Communications (SPCOM 2018), 16--19 July, 2018, Indian Institute of Science, Bangalore, India.

(*) Congrats to Bheemappa Halavar for their paper acceptance:"Accurate Performance Analysis of 3D Mesh Network on Chip Architectures". To appear in the IEEE CONECCT 2018.

(*) Congrats to Pramod Yelmewad for their paper acceptance:"Near Optimal Solution for Traveling Salesman Problem using GPU". To appear in the IEEE CONECCT 2018.

(*) Congrats to Khyamling Parane and Prabhu Prasad B M for their paper acceptance:"FPGA based NoC Simulation Acceleration Framework Supporting Adaptive Routing". To appear in the IEEE CONECCT 2018.

(*) (*)18-Dec-2017. Pramod and Parth present their poster "Parallel Computation of Iterative Hill Climbing Algorithm Algorithm to Solve TSP" at the HiPC 2017 Student Research Symposium.

(*) 18-Dec-2017. Academic Birds-of-Feather Session on "gem5 Simulation using POWER ISA v3.0" at the HiPC 2017 conference by Basavaraj Talawar, Sandipan Das, IBM ISDL and Gautham Shenoy, IBM ISDL.

(*) 19-September-2017. Congrats to Khyamling Parane and Prabhu Prasad B M for their paper acceptance: YaNoC: Yet another Network on Chip Simulation Acceleration Engine using FPGAs. To appear in the 31st International Conference on VLSID 2018.

(*) 15-July-2017. Basavaraj Talawar, delivers a special lecture on "FPGA Accelerated Computer System Simulation" at Amrita University, Bangalore.

(*) "FPGA based simulation acceleration for Network-on-Chips" Research Paper presented at INDOSYS 2017, held at IIT Bombay
http://cds.iisc.ac.in/faculty/simmhan/indosys-2017/

(*) Prabhu Prasad B. M and Khyamling Parane, Attended workshop on "Core VLSI Design" Organized by E&ICT Academy IIT Guwahati held on 4-9 April, 2017 at NIT Sikkim
http://eict.iitg.ernet.in/faculty_development.html

(*) Signing off the MoU between IBM India (ISDL) and NITK. IBM India in the News - December 22, 2016 | YourStory
https://yourstory.com/2016/12/ibm-nitk-collaborative-research-projects/

(*) 25-Nov-2016. IBM-ISDL MoU to establish NITK-IBM Computer Systems Research Group.

(*) 23-Nov-2016. Sreepathi Pai, post-doctoral researcher from ICES, UT-Austin visited to SPARK Lab.
https://users.ices.utexas.edu/~sreepai/

(*) 15-Nov-2016. Basavaraj T is invited to speak on "History of Modern Computing" in the Institute of Engineers - Mangalore Local Centre's Lecture Meeting.

(*) "HiMesh : A Low Power High Performance Improved Architecture for 3-D On-Chip Networks" paper accepted at Student Research Symposium, HiPC-2016, congrats to Anagh Singh and Anamik Sarvaiya

(*) "Fast Large Graph Algorithms on GPU" paper accepted at Student Research Symposium, HiPC-2016, Congrats to Ankur Anandapu

(*) "On-Chip Network simulation acceleration using FPGAs" paper accepted at Student Research Symposium, HiPC-2016, Congrats to Khyamling and Prabhu prasad B M

(*) "Cache Analysis and Software Optimizations for Faster On-Chip Network Simulations" paper accepted at ICIIS, IIT Roorkee,Congrats to Khyamling and Prabhu prasad B M http://www.iciis2016.org/

(*) Congrats to sandipan, Vivek, Swapnil for getting placed in IBM, Aryaka Networks, Amdocs.

(*) July, 2016: IBM Systems and Technology Group - Linux Technology Center starts mentoring Sandipan, Vivek and Swapnil for Power on QEMU and GEM5 projects.

(*) July, 2016: Congrats to Ankur, Arun, Dinesh, Ranjith, Jagadish on completing their M.Tech degrees.

(*) June, 2016: SPARK Website up.

(*) June, 2016: DST-SERB funding for the FPGA based simulation acceleration project received.

(*) May, 2016: AMD APU machine procured.

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