Current Research

Machine Learning based Performance and Power prediction of NoCs

Performance accurate software simulators are generally too slow for interactive use. We are building a machine learning framework that uses existing results of the simulators (Booksim 2.0 and Orion) and predicts the overall performance and power of the NoC. Such a framework can potentially save simulation time while evaluating options from a large design space.

People Involved: Anil Kumar

Design of an Efficient 3D-NoC Architecture for Modern Processors

NoCs on 3D ICs technology provides an opportunity to better the on chip communication delay, energy and area parameters compared to the 2D-NoCs. We are extending the existing simulators to support 3D-NoC topologies. Design space exploration of 3D-NoC is being driven by considering physical characteristics of vertical connections like Through Silicon Vias (TSVs). The exploration is aided using power, performance and cost metrics such as area, throughput, avg. flit latency, Energy per bit transferred, and EDP.

People Involved: Bheemappa Halavar

On-Chip Network simulation acceleration using FPGA

NoC researchers have relied on cycle accurate power and performance simulators (viz. Orion, Garnet, Noxim, SICOSYS, Booksim) to explore the micro-architectural design space of on-chip networks. The NoC parameters such as topology, routing algorithm, flow control, and router micro-architecture, including buffer management and allocation schemes can be analyzed using these simulators. Large scale design space exploration of NoCs can be very time-intensive. To address this issue we propose hardware based acceleration using FPGA to speed up the NoC simulation. Fast and accurate simulators provide a vehicle for the rapid exploration of microprocessor designs. FPGAs are made up of thousands of small interconnected lookup tables that can be used to iterate easily in an incremental design debug cycle similar to software development life cycle. Therefore, FPGA accelerated simulators are faster than the software-only simulators.

People Involved: Khyamling Parane and Prabhu Prasad B M.

GPU-based heuristic approaches to solve TSP

Traveling Salesman Problem (TSP) is an NP-hard, O(n!) , combinatorial optimization problem. The time complexity of TSP is factorial time when solved using brute-force method and exponential time when solved using dynamic programming. For its large number of applications in science and engineering, time efficient TSP solutions are of great importance. Since exact methods are prohibitive for large city instances, heuristic approaches gives a near-optimal solution by exploring limited search space in a reasonable amount of time. Although heuristic methods to solve TSP are faster than the exact methods, the execution time increases as input size increases. For large input sizes, GPU implementation of TSP have been shown to complete in a reasonable amount of time.

People Involved: Pramod Yelmewad

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