Welcome to the SPARK Lab

A warm and hearty welcome to fellow researchers, students and enthusiasts. Our research is focused on the areas of Network on chips(NoC), High Performance Computing and Computer Architecture.

Our Motto: Better Future for Computing!

SPARK Team, From (R2L) Vivek, Anil, Sandipan, Swapnil,
Basavaraj T, Bheem, Pramod, Prabhu, Khyam

On Going Projects

As Moore's law continues to prevail, more cores and components have been crammed onto a single die. The surge in on-chip communication has lead to a structured hardware communication framework - the Network-on-Chip. Our group focusses on various issues in this challenging and exciting area.

Machine Learning based Performance and Power prediction of NoCs

Performance accurate software simulators are generally too slow for interactive use. We are building a machine learning framework that uses existing results of the simulators (Booksim 2.0 and Orion) and predicts the overall performance and power of the NoC.

Design of an Efficient 3D-NoC Architecture for Modern Processors

NoCs on 3D ICs technology provides an opportunity to better the on chip communication delay, energy and area parameters compared to the 2D-NoCs. We are extending the existing simulators to support 3D-NoC topologies.

On-Chip Network simulation acceleration using FPGA

Large scale design space exploration of NoCs can be very time-intensive. To address this issue we propose hardware based acceleration using FPGA to speed up the NoC simulation. Fast and accurate simulators provide a vehicle for the rapid exploration of microprocessor designs. FPGAs are made up of thousands of small interconnected lookup tables that can be used to iterate easily in an incremental design debug cycle similar to software development life cycle.

Research Funding

  • Project Title: Design of a Modular, FPGA Accelerated, Chip Multiprocessor Architecture Simulator. Source: DST-SERB Young Scientist Fellowship. 2016 - 2018.
Leased Line IP : Load Balanced